Pascal and Francis Bibliographic Databases

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A 10μs fast switching PLL synthesizer for a GSM/EDGE base-stationKEAVENEY, Mike; WALSH, Patrick; TUTHILL, Mike et al.IEEE International Solid-State Circuits Conference. 2004, pp 192-193, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Theorie des PLL mit Rechteckcharakteristik das Phaseudetektors und PI-Zegelfilter. I = Theory of the PLL with rectangular phase detector characteristic and with PI control filter. IHOFFMANN, M. H. W.Frequenz. 1989, Vol 43, Num 6, pp 167-171, issn 0016-1136, 5 p.Article

A novel phase-lock loop acquisition performance measureHASAN, P.AEU. Archiv für Elektronik und Übertragungstechnik. 1986, Vol 40, Num 6, pp 405-407, issn 0001-1096Article

Chaos from phase-locked loops. II: High-dissipation caseENDO, T; CHUA, L. O; NARITA, T et al.IEEE transactions on circuits and systems. 1989, Vol 36, Num 2, pp 255-263, issn 0098-4094, 9 p.Article

A phase-locked loop for driving vibrating tube densimetersWOOD, R. H; BUZZARD, C. W; MAJER, V et al.Review of scientific instruments. 1989, Vol 60, Num 3, pp 493-494, issn 0034-6748Article

Digital phase-locked loop with jitter boundedWALTERS, S. M; TROUDET, T.IEEE transactions on circuits and systems. 1989, Vol 36, Num 7, pp 980-987, issn 0098-4094, 8 p.Article

Loop gain compensation in phase-locked loopsYEAGER, R.RCA review. 1986, Vol 47, Num 1, pp 78-87, issn 0033-6831Article

A fully integrated 13GHz ΔΣ fractional-N PLL in 0.13μm CMOSTIEBOUT, Marc; SANDNER, Christoph; WOHLMUTH, Hans-Dieter et al.IEEE International Solid-State Circuits Conference. 2004, pp 386-387, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Modeling of chaotic characteristics in integrated phase-locked loopSIU, W. K; WONG, H; CHEUNG, T. S et al.International conference on microelectronic. 1997, pp 751-754, isbn 0-7803-3664-X, 2VolConference Paper

Secure random number generation using chaotic circuitsBERNSTEIN, G. M; LIEBERMAN, M. A.IEEE transactions on circuits and systems. 1990, Vol 37, Num 9, pp 1157-1164, issn 0098-4094, 8 p.Article

Dynamic clamp for pull-in time reductionCALLEJA, H.IEEE transactions on instrumentation and measurement. 1996, Vol 45, Num 5, pp 907-909, issn 0018-9456Article

Multiple cochannel interference effects in a first-order phase-locked loopHASAN, P.European transactions on telecommunications and related technologies. 1994, Vol 5, Num 3, pp 319-326, issn 1120-3862Article

New algorithms for hyperbolic radionavigationFISHER, A. J.IEE proceedings. Part F. Radar and signal processing. 1993, Vol 140, Num 2, pp 145-152, issn 0956-375XArticle

Locking response in coupled phase systemsKOZLOV, A. K.Radiophysics and quantum electronics. 1993, Vol 36, Num 8, pp 552-554, issn 0033-8443Article

The dynamics of a delayed phase-locked loop systemEFREMOV, I. A; UDALOV, N. N.Telecommunications & radio engineering. 1990, Vol 45, Num 3, pp 114-116, issn 0040-2508Article

A phase locked motor speed control system with a sample-and-hold phase detectorLAOPOULOS, T. L; KARYBAKAS, C. A.IEEE transactions on industrial electronics (1982). 1988, Vol 35, Num 2, pp 245-252, issn 0278-0046Article

A new pattern jitter free frequency error detectorALBERTY, T; HESPLET, V.IEEE transactions on communications. 1988, Vol 37, Num 2, pp 159-163, issn 0090-6778Article

An integral measure of the phase noise power in phase locked loopsARTIUCH, R.AEU. Archiv für Elektronik und Übertragungstechnik. 1987, Vol 41, Num 5, pp 289-293, issn 0001-1096Article

Second-order PLL loop filters with independent adjustment of ωn and ζDEKKER, A. P.Electronics Letters. 1986, Vol 22, Num 22, pp 1196-1197, issn 0013-5194Article

Analysis of the effects of time delay in clock recovery circuits based on phase-locked loodsZIBAR, Darko; OXENLØWE, Leif K; CLAUSEN, Anders T et al.Lasers and Electro-optics Society. 2004, isbn 0-7803-8557-8, 2Vol, Vol1, 316-317Conference Paper

Modeling of nonlinear dynamics of phase-system cascadingKORZINOVA, M. V; MATROSOV, V. V.Radiophysics and quantum electronics. 1993, Vol 36, Num 8, pp 555-558, issn 0033-8443Article

Control of the duration of the transients in a digital phase locked loop systemBRYUKHANOV, YU. A.Telecommunications & radio engineering. 1992, Vol 47, Num 7, pp 13-16, issn 0040-2508Article

10GHz GaAs JFET dual-modulus prescaler ICKASAHARA, J; WADA, M; KAWASAKI, H et al.Electronics Letters. 1989, Vol 25, Num 14, pp 889-890, issn 0013-5194, 2 p.Article

False lock and bifurcation in Costas loopsSTENSBY, J.SIAM journal on applied mathematics (Print). 1989, Vol 49, Num 2, pp 420-431, issn 0036-1399, 12 p.Article

Gain-weighted technique for directly measuring loop bandwidth of split-loop phase-locked loopKENINGTON, P. B; EDWARDS, D. J; MCGEEHAN, J. P et al.Electronics Letters. 1989, Vol 25, Num 3, pp 180-182, issn 0013-5194, 3 p.Article

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